(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a high performance CMOS device at a lower fabrication cost as a result of reduced masking procedures.
(2) Description of Prior Art
Micro-miniaturization, or the ability to fabricate semiconductor devices comprised with sub-micron features, has allowed device performance to be increased. Complimentary metal oxide semiconductor (CMOS) devices, comprised with both N channel (NMOS), and P channel (PMOS) elements have benefited, in terms of increased performance, as a result of micro-miniaturization. The fabrication costs for CMOS devices however have remained extensive due to the numerous masking procedures needed. This invention will describe a novel fabrication sequence for a CMOS device in which performance increases are realized while the fabrication cost can be reduced when compared to counterpart CMOS devices achieved without the use of this present invention. The decrease in CMOS fabrication cost is achieved via a reduction in photolithographic masking steps. Novel procedures featuring disposable spacers allow several photolithographic masking steps that are used with counterpart CMOS devices fabricated without the use of this invention, to be eliminated. Prior art such as Pradeep et al, in U.S. Pat. No. 6,346,468 B1, Ang et al, in U.S. Pat. No. 6,319,783 B1, Pradeep et al, in U.S. Pat. No. 6,251,764 B1, Zhou et al, in U.S. Pat. No. 6,156,598, and Yu, in U.S. Pat. No. 6,348,387 B1, describe L-shaped spacers as well as lightly doped source/drain regions formed through L shaped spacers. However none of the prior art describe the novel process sequence described in the present invention in which a combination of L shape, and disposable spacers are used to reduce the number of photolithographic masking procedures used to fabricate both the NMOS and PMOS elements of a CMOS device.
It is an object of this invention to reduce the processing cost of a metal oxide semiconductor field effect (MOSFET) device, via a reduction in the number of photolithographic masking steps used for fabrication of the device.
It is another object of this invention to apply the cost savings realized via reduction of photolithographic masking procedures, to the fabrication of CMOS devices comprised with both NMOS and PMOS elements.
It is still another object of this invention to use a partially removed spacer structure, in combination with ion implantation procedures performed at various implantation angles, to allow several features of the NMOS and PMOS elements to be formed using a minimum of photolithographic masking procedures.
It still yet another object of this invention to allow a process used to restore the partially removed spacer structure to allow a salicide procedure to be selectively performed in specific regions of the CMOS elements.
A method of fabricating a CMOS device, featuring a reduction in processing costs achieved via the reduction in photolithographic masking procedures, is described. After formation of a gate structure on an underlying gate insulator layer in regions of a semiconductor substrate to be used for the NMOS and for the PMOS elements of a CMOS device, a first insulator spacer comprised of an underlying silicon oxide layer and an overlying silicon nitride shape is formed on the sides of the gate structure. Removal of the silicon nitride shape results in a silicon oxide L shaped spacer comprised with a thick silicon oxide portion in a region underlying a previously removed silicon nitride shape, and comprised with a thinner silicon portion on regions exposed to the spacer definition and silicon nitride removal procedures. After formation of a block out mask on a specific CMOS element, a series of implantation procedures are performed to form the halo, lightly doped source/drain (LDD), and heavily doped source/drain regions, for an exposed CMOS element. The halo region is formed using a high angle implantation, while a lower angle implantation procedure results in an LDD region underlying the thick silicon oxide portion, and results in a deeper, heavily doped source/drain region located underlying the thinner silicon oxide portion. The same procedure, block out mask, and series of implantation procedures are then used to form similar features for the previously blocked CMOS element. Formation of silicon nitride shapes on L shaped spacers, featuring silicon nitride extensions overlying halo, LDD and heavily doped source/drain regions in regions of a specific CMOS device, allow other non-protected regions of the another specific CMOS device to experience salicide formation on exposed source/drain and gate regions.